Performance Analysis of Dual Material Junction Accumulation Mode tri gate Junctionless SOI FET: Modeling and Simulation

The paper illustrates the performance of Tri-Gate (TG) Dual Material (DM) SOI (Silicon on Insulator) Junctionless (JL) FET operating in Junction Accumulation Mode (JAM). An analytical model is developed to evaluate its performance. device also simulated using Silvaco simulator. Both and simulation results are compared found match closely. Quasi 3-D modeling approach adopted here determine surface potential above device. In this technique, entire segregated into two 2-D devices with certain physical constraints. These then analyzed separately obtain potentials, which added together suitable multiplication factors get This is, turn, used threshold voltage, sub-threshold drain current (Id,sub) induced barrier lowering (DIBL). proposed configuration reduces IOFF significantly offers excellent immunity SCEs. response studied for variations parameters, such as, thickness High-K dielectric layer stack gate, channel doping, work-functions as well lengths gate metals. Such study will lead turn immune short effects through proper choice various parameters.